KEYSIGHT SPOTLIGHTS SOLUTIONS ENABLING BETTER AI INFRASTRUCTURE AT DESIGNCON 2024
Keysight will present the following sessions at DesignCon 2024: Keysight Education Forum (KEF), technical presentations/papers, and more.
Keysight empowers innovators to accelerate the development of intelligent networks by pushing the boundaries of current data speeds. At DesignCon 2024, from January 30 – February 1, 2024, Keysight will demonstrate its market-leading design, simulation, and test solutions that enable electrical/optical transmission and data centre interconnect applications to speeds of 800G and 1.6T.
Join Keysight experts at Booth #1039 for the following demonstrations:
UCIe Chiplet PHY Designer – As AI workloads evolve and change, chiplet based system architectures can be used to scale up quickly to keep pace with the growing compute needs. This demo will showcase a new PHY designer for chiplets that allows the modeling, simulation, and analysis of the high-speed channel between two D2D PHY interfaces.
Enabling PCIe 7.0 Technology – PCIe architecture provides a robust high-bandwidth interconnect solution for attaching compute chips and network devices used in AI / ML applications. It also has the added benefit of a mature ecosystem that has been built up to include a compliance testing framework to ensure interoperability between different vendors. This will demonstrate Keysight's solutions that can be used to enable the testing of PCI Express 7.0 transmitter and receiver technologies.
PCIe 6.0 and CXL 2.0 Solutions – The rapid deployment of AI accelerators for use in compute arrays has driven the demand for higher speed PCIe chip-to-chip interfaces. Keysight's PCIe 6.0 Analyzer and PCIe 6.0 Exerciser solutions will be used to show how live PCIe 6.0 protocol traffic can be generated and analyzed using advanced triggers and filters while emulating both root complex and endpoint scenarios.
1.6T 212G PHY Transmitter/Receiver Testing – In order to process the large datasets associated with AI and large language models, bandwidth improvements are needed in both the compute-oriented interfaces as well as those used to enable higher speed data networks. Keysight will demonstrate the testing and validation of next-gen SerDes designs running at 212 Gbps per lane which are used to enable high-performance computing to unleash the potential of AI.
Test USB4 in Record Time – This demonstration spotlights Keysight's test solution for USB4 transmitter, receiver, and return loss as well as test automation software featuring measurement acceleration technology to provide the fastest time-to-answer in the market.
Signal Integrity PLTS 2024 – With an increase in demand for high-speed digital designs and interconnects aimed at enabling AI / ML applications, there are new signal integrity design and measurement challenges to consider. This demonstration will highlight vector network analysis and time domain reflectometry measurement solutions Keysight has developed to address these new challenges.
DDR5 Simulation and Test – AI / ML implementations impose challenging throughput demands on DRAM memory resources which has driven the adoption of DDR5 designs. Keysight will demonstrate a validation solution for DDR5 as well as a new high bandwidth and low noise probing solution which can be used to accurately report the Tx and Rx performance of next-gen memory designs.
Keysight at DesignCon 2024